A stacked memory device in which a plurality of memory chips each including a dynamic random access memory (DRAM) circuit is stacked by coupling the memory chips via through silicon via (TSV) repeatedly performs a refresh operation at regular time intervals such that stored contents (data) are not lost due to discharge from a storage element of the DRAM circuit. Because the higher temperature becomes, the higher a discharging rate of discharge of electric charges from the storage element of the DRAM circuit becomes, the stacked memory device sets a uniform shortest refresh interval for the entire device such that the refresh interval is suitable for a memory block having the highest temperature inside of the device and executes a refresh operation, but as the temperature increases, the refresh interval is reduced to increase execution frequency.
A technology in which, in a stacked memory device in which a plurality of memory chips is stacked by coupling the memory chips via TSV, a temperature sensor circuit is disposed in each memory chip to output temperature information of the memory chip to the outside of the device, a refresh interval is externally set for each memory chip, based on the temperature information, and a refresh operation is performed has been proposed.
In the stacked memory device, a temperature difference occurs inside of the device due to an influence, such as an operation state of an inner circuit, heat generation of an LSI disposed therearound, or the like, and, even in a part in which temperature is low and the refresh interval may be long, the shortest refresh interval is set, and thereby, the execution frequency of the refresh operation is increased, so that power consumption of the stacked memory device is increased.
The following is a reference document.
[Document 1] Japanese Laid-open Patent Publication No. 2012-142576.